1. Field of the Invention
The present invention relates to a method of forming a contact structure in a semiconductor device, and more particularly, to a method of forming a contact structure on a semiconductor substrate containing fine recesses and projections.
2. Description of the Prior Art
First, an example of a conventional contact structure provided in a semiconductor device is described below, specifically the process for connecting metallic wires to diffusion regions formed on the surface of a semiconductor substrate.
FIG. 1(a) is a plan view of an SCC type dynamic RAM a sectional view of the SCC type dynamic RAM cell taken along line Vb--Vb in FIG. 1(a). The cell contains a Contact structure between the drain diffusion region of a transfer transistor and a bit line. The reference numeral 1 shown in FIG. 1(b) designates a silicon substrate, the reference numeral 2 designates an active region, the reference numeral 3 designates a transfer transistor, the reference numeral 4 designates a drain diffusion region, the reference numeral 5 designates a separation trench, the reference numeral 6 designates a capacitance trench, the reference numeral 7 designates a polycrystalline silicon film available for a word line, and the reference numeral 8 designates a silicon oxide (SiO2) film for composing a word line. The reference numeral 9 designates a word line which is composed of the polycrystalline silicon film 7 and the silicon oxide film 8. Further, the reference numeral 10 designates a side-wall insulation film, the reference numeral 11 designates a ground silicon oxide film, the reference numeral 13 designates a BPSG film, the reference numeral 14 designates a contact hole, the reference numeral 16 designates another polycrystalline silicon film for composing a bit line 18, and the reference numeral 17 designates a tungsten silicide (WSi.sub.x film. The bit line 18 is composed of the polycrystalline silicon film 16 and the tungsten silicide film 17. In the event a reference numeral is not shown in subsequent drawings, reference should be made to FIG. 1(b) for clarification.
Referring now to FIG. 2(a)-2(c), a first example of a conventional method of forming a contact hole is described below. As shown in FIG. 2(a), first, a synthetic film composed of the silicon oxide film 11 and the BPSG film 13 is deposited on the silicon substrate 1 which has fine recesses and projections on the surface and the diffusion drain region 4 (not shown) under the surface. In this case, the silicon oxide film 11 is deposited on the silicon substrate 1 in order to suppress the diffusion of boron and phosphor from the BPSG film 13 to the silicon substrate 1.
Next, as shown in FIG. 2(b), by using reactive ion etching process with a mask of contact-hole resist pattern 21 the contact hole 14 is provided through the silicon oxide film 11 and the BPSG film 13, so that the surface of the silicon substrate 1 can be exposed at the bottom of the contact hole 14. The diffusion drain region 4 (not shown) is to be formed on the surface of the silicon substrate 1 later on.
Next, as shown in FIG. 2(c), the contact-hole resist pattern 21 (not shown) is removed, and then, residue is removed from the surface of the silicon substrate 1 exposed on the bottom of the contact hole 14 by executing an etching process in solution containing buffered fluoric acid for example. Then, by applying a CVD (chemical vapor deposition) process, for example, the polycrystalline silicon film 16 for the bit line 18 is deposited on the surface of the contact hole 14. While executing the CVD process, conventionally, the temperature in a reactor tube is cooled to be 300.degree. C. or less in order to prevent the surface of the silicon substrate 1 from oxidizing itself again, when the silicon substrate 1 is inserted. Alternatively, a CVD apparatus under reduced pressure is made available so that oxygen can be prevented from leaking into the CVD apparatus when the silicon substrate 1 is inserted. Next, an oxidized film is removed from the surface of the polycrystalline silicon film 16 with the etching process for example in a solution of buffered fluoric acid, and then, the tungsten silicide film 17 is deposited on the polycrystalline silicon film 16 for the bit line.
Next, arsenic is implanted into the synthetic film composed of the polycrystalline silicon film 16 and the tungsten silicide film 17, and then, a patterning process is executed for the pattern of the bit line 18 by applying a resist pattern. Next, thermal treatment at 900.degree. C. for 30 minutes is performed, so that arsenic diffuses itself over the superficial region of the silicon substrate 1, which is in contact with the bit line 18, to form the diffusion drain region 4 (not shown). Thus, the contact structure shown in FIG. 1 is obtained.
FIG. 3 shows a sectional view of a second example of a conventional contact structure between the bit line 18 and the drain diffusion region 4 of a transfer transistor 3 in the SCC type dynamic RAM cell produced by using the first conventional method. In the contact structure shown in the first example, the size of the contact hole of the second example is enlarged to a degree so as to be formed easily by reducing the side-wall insulation film 10 on the side of the contact hole 14.
FIG. 4 shows a sectional view of a third example of a conventional contact structure between the bit line 18 and the drain diffusion region 4 of a transfer transistor 3 built in the SCC type dynamic RAM cell also provided by using the first conventional method. The third example provides a polycrystalline silicon film 12 as the etching stopper on the side of the contact hole 14 of the silicon oxide film 8 for the word line in the second example. For example, this prior art was disclosed by T. Taga et al., Extended Abstracts of 19th SSDM, pages 15-18, 1987.
Next, by referring to FIGS. 5(a)-5(f), a second conventional method of forming a contact structure of the third example is described below. As shown in FIG. 5(a), first, a silicon oxide film 11 is deposited on a silicon substrate 1 which superficially contains fine recesses and projections. Next, as shown in FIG. 5(b), a first contact resist pattern 19 having an aperture corresponding to a contact hole 14 is formed on the silicon oxide film 11. Next, the silicon oxide film 11 exposed to the aperture of the first contact resist pattern 19 is removed by applying a reactive ion etching process.
Next, as shown in FIG. 5(c), after the first contact hole resist pattern 19 (not shown) is removed, the polycrystalline silicon film 12 acting as an etching stopper is deposited on the silicon oxide film 11 and then, ionized arsenic is implanted into the polycrystalline silicon film 12.
Next, a resist pattern 20 of the etching stopper is formed in a region of the polycrystalline silicon film 12 where the contact hole 14 (not shown) is to be formed. Next, as shown in FIG. 5(d), the polycrystalline silicon film 12 acting as the etching stopper is removed, except for that portion of the polycrystalline silicon film 12 corresponding to the position of the resist pattern 20 (not shown), and then the resist pattern 20 is also removed. Next, a BPSG film 13 is deposited on the remaining polycrystalline silicon film 12 and the silicon oxide film 11. Next, a thermal treatment is applied to the deposited BPSG film 13 causing this film to fluidify in order to level off the uneven surface of the silicon substrate 1. At the same time, arsenic diffuses itself in the superficial region of the silicon substrate 1 which contacts the polycrystalline silicon film 12 acting as the etching stopper. As a result, the drain diffusion region 4 is formed on the surface of the silicon substrate 1.
Next, as shown in FIG. 5(e), a second contact-hole resist pattern 22 having an aperture corresponding to the contact hole 14 is formed, and the BPSG film 13 exposed to the aperture region is removed. In this case, the polycrystalline silicon film 12 can effectively function as the etching stopper. More particularly, even when the thickness of the polycrystalline silicon film 12 is decreased to less than one fifth the thickness of the BPSG film 13 and even when the etching time is set enough to remove the BPSG film 13 completely, the silicon oxide film 11 above the word line 9 can fully be prevented from being subjected to the etching process. By using this technique, even after the contact hole 14 is expanded to such a dimension that allows the processing to be done easily, no short-circuit can be generated between the bit line 18 (not shown) and the word lines 9.
Next, as shown in FIG. 5(f), first, the second contact-hole resist pattern 22 (not shown) is removed, and then, the residue is removed from the surface of the polycrystalline silicon film 12 exposed to the contact hole 14 by executing an etching process, for example with a solution of buffered fluoric acid.
Next, a polycrystalline silicon film 16 available for composing a bit line 18 is deposited on the surface of the BPSG film 13 by applying, for example, a CVD process under reduced pressure. In this case, in order to suppress the reoxidization of the exposed surface of the polycrystalline silicon film 12 functioning as the etching stopper, the internal temperature of the reactor tube is cooled at 300.degree. C. or less, when the silicon substrate 1 is inserted into it. Alternatively, a CVD apparatus under reduced pressure is used in order to prevent oxygen from infiltrating into the reactor tube when the silicon substrate 1 is inserted into it. Next, an oxide film is removed from the surface of the polycrystalline silicon film 16 of the bit line 18 by executing an etching process, for example, with a solution containing buffered fluoric acid.
Next, a tungsten silicide film 17 is deposited on the polycrystalline silicon film 16 for the bit line 18 by means of a sputtering process for example. Next, arsenic is implanted into the synthetic film composed of the polycrystalline silicon film 16 and the tungsten silicide film 17, and then, by using a resist pattern, a patterning process is applied to the pattern of the bit line 18 to complete the formation of the contact structure shown in FIG. 4.
Nevertheless, as still finer dimensions of semiconductor devices have recently been required, there are many cases requiring formation of contacts in recessed regions of a silicon substrate having extremely fine recesses and projections. For example, when manufacturing a DRAM cell of 4-16 Mbits or more (refer for example Fuse et al., the proceeding of the 19th Solid Element and Material Conference, P11 (Tokyo in Aug., 1987)), it is necessary to precisely form a contact between the drain diffusion region of the transfer transistor and the bit lines in a space between word lines which adjoin each other at one .mu. or less of interval.
When such a contact is formed by applying the first conventional method described above, it is essential to provide extremely small dimensions of the contact hole 14 in order to prevent the bit line 18 from coming into contact with the word lines 9. Therefore, the formation is difficult. Concretely, by assuming 1.4.mu. of the bit-line pitch and 1.6.mu. of the word-line pitch in order to manufacture a 16 Mbit DRAM, it is necessary to minimize the dimensions of the contact hole 14 to about 0.4.mu. square in order that the silicon oxide film 8 on the word line 9 can be prevented from being subject to etching even when the position of masking deviates.
Although the first conventional method can provide 0.5 or 0.6.mu. square for the contact hole 14, it is very difficult to provide 0.4.mu. square for the contact hole 14 by operating any conventional light-exposure device which is available for the manufacture of 16 Mbit DRAM.
On the other hand, in the second example shown in FIG. 3, the silicon oxide film 8 for the word line 9 is subjected to etching when the BPSG film 13 and the silicon oxide film 11 exposed to the aperture of the contact-hole resist pattern 21 are removed, to expose partially the polycrystaline silicon film 7 for the word line. Therefore, electrical short-circuit is liable to occur between the bit line 18 and the word line 9.
Additionally, the silicon oxide film 8 is not etched in the second conventional method. Thus, the second conventional method needs to repeat the etching processes twice, and further it includes two processes to deposit polycrystalline silicon film which require care for suppressing the re-oxidization of the surfaces of the exposed silicon substrate or polycrystalline silicon film. In other words, the conventional second method involves extremely complex processes.
Furthermore, according to the second conventional method, since the polycrystalline silicon film 12 acting as the etching stopper is present between the drain diffusion region 4 and the bit line 8, it is quite difficult to secure a stable electrical connection.
Kusters et al. disclosed a method of forming a contact in RAM with use of a wet etching process (Symp. VLSl Tech. Dig. (1987) p93) wherein a nitride layer serves as an etch stop. Auer et al. discloses a method of forming a DRAM wherein a polysilicon is used as an etch stop and the polysilicon is oxidized completely (Extended Abstracts of 22nd Conf on Solid State Devices and Materials, 1990, P401). However, short-circuit is liable to happen in these methods.